The present invention relates generally to high speed circuits where the timing of signals occurring in a main path and an auxiliary path, such as in a feedback path, is critical. Although not limited to such an application, one circuit type where this is particularly true is a sample-and-hold circuit. Sample-and-hold circuits are often used on the input of an analog-to-digital converter for providing a stable input signal for the converter. High speed converters are becoming very common as digital signal processing of high frequency signals is undertaken.
Sample-and-hold circuits typically employ an analog switching device, generally referred to as a sampling gate, for periodically connecting a capacitor to an input signal to be sampled. During the tracking state, the capacitor is connected to the signal so that it charges and discharges to track the voltage level of the signal. In the hold state, the switch is turned off, disconnecting the capacitor from the input signal. The capacitor holds that voltage level existing on the input signal at the time the capacitor is disconnected. The charge on the capacitor should stay constant, providing a constant output voltage.
The capacitor is also typically connected to a high impedance input of a buffer amplifier which provides the hold output signal of the sample-and-hold circuit, the high impedance input ensuring minimal discharge of the capacitor during the hold phase of the circuit operation.
The switches used in sample and hold circuits are typically either Schottky diode bridges or field-effect transistors. The diode bridge, which is perhaps the simplest of the switches, is switched by a pair of controlled current sources. These basic circuits however have significant blow-by distortion caused by the input signal coupling to the output during the hold state due to diode capacitances.
This has been improved upon by the addition of a diode at each corner of the bridge associated with the current sources. A fixed bias is applied to the diodes to provide a low impedance path to ground for the blow-by current in the hold state. Since the bias is fixed, though, the charge injected into the hold capacitor at the switching off of the diode bridge varies with the magnitude of the input signal disproportionately, thereby producing nonlinearity in the relationship of the held charge on the input signal represented by it.
This in turn has been overcome in conventional circuits by bootstrapping the bias voltage from the sample-and-hold output. Such a circuit is shown generally at 10 in FIG. 1. Circuit 10 includes an input terminal 12 for receiving the input signal to be sampled. This terminal is connected to an input buffer amplifier 14.
The output of amplifier 14 is input into a Schottky diode bridge 1 which is controlled by a pair of current sources 20 and 22. These current sources receive a control signal from a control signal generator 23. The diode bridge adjacent each current source has blow-by current shunt diodes 24 and 26 which are biased by fixed voltage sources 28 and 30. The output of the switch is coupled to a hold capacitor 32, one side of which is grounded. This capacitor tracks the input signal during the track state and holds a charge proportional to the input signal when in the hold state. The capacitor is coupled to output amplifier 34 for outputting the output signal on an output terminal 36. As has been mentioned, the bias voltages for diodes 24 and 26 are bootstrapped from the circuit output through a bias circuit 38.
This circuit configuration is more effective than prior versions of the circuit. However, in high speed applications, it tends to have limited use because of the longer settling time required by the bootstrapping arrangement. This is due primarily to the time delay in the signal propagating to the output and then feeding back to the operative circuit component, such as the switch or amplifier.
Conventional sample-and-hold circuits also typically have a hold capacitor which is grounded so that it must take the complete charge of the input signal. Thus, changes in charge take more time than if less stored charge was required.